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A Reliable LDMOS Transistor Based on GaN and Si3N4 Windows in Buried Oxide | ||
Computational Sciences and Engineering | ||
دوره 2، شماره 2، آذر 2022، صفحه 291-297 اصل مقاله (159.63 K) | ||
نوع مقاله: Original Article | ||
شناسه دیجیتال (DOI): 10.22124/cse.2023.23833.1049 | ||
نویسندگان | ||
Mahsa Mehrad* ؛ Meysam Zareiee | ||
School of Engineering, Damghan University, Damghan, Iran | ||
چکیده | ||
High breakdown voltage and reduced specific on-resistance are obtain in the new LDMOS structure with wide band gap material in the buried oxide. GaN with higher mobility and wider band gap energy than silicon is an important material that causes better performance in power devices. Moreover, self-heating effects of the proposed LDMOS structure is controlled using two other Si3N4 windows at the top and bottom of the GaN window. Our simulation with two-dimensional ATLAS simulator shows that the proposed three windows in buried oxide of the LDMOS transistor (TW-LDMOS) has better reliability than conventional LDMOS (C-LDMOS) structure due to the flexible behavior of the TW-LDMOS in higher drain voltages and reduced electron temperature. | ||
کلیدواژهها | ||
LDMOS؛ GaN؛ Breakdown voltage؛ Hot electron effect | ||
مراجع | ||
[1] X. Luo, B. Zhang, and Z. Li, “New high-voltage (> 1200 V) MOSFET with the charge trenches on partial SOI,” IEEE Trans. Electron Devices, vol. 55, no. 7, pp. 1756–1761, 2008.
[2] A. A. Orouji and M. Mehrad, “Breakdown voltage improvement of LDMOSs by charge balancing: An inserted P-layer in trench oxide (IPT-LDMOS),” Superlattices Microstructure., vol. 51, no. 3, pp. 412–420, 2012.
[3] M. Mehrad, “Inserting Different Charge Regions in Power MOSFET for Achieving High Performance of the Electrical Parameters,” Silicon, vol. 13, no. 4, pp. 1107– 1111, 2021.
[4] Y. Wang, B. Duan, L. Sun, X. Yang, Y. Huang, and Y. Yang, “Breakdown point transfer theory for Si/SiC heterojunction LDMOS with deep drain region,” Superlattices Microstructure., vol. 151, no. December 2020, p. 106810, 2021.
[5] Z. Ramezani, A. A. Orouji, “A silicon-on-insulator metal-semiconductor field-effect transistor with an L-shaped buried oxide for high output-power density,” Materials Science in semiconductor Processing, vol. 19, pp.124-129, 2014.
[6] Z. Dong, B. Duan, C. Fu, H. Guo, Z. Cao, and Y. Yang, “Novel LDMOS Optimizing Lateral and Vertical Electric Field to Improve Breakdown Voltage by Multi-Ring Technology,” IEEE Electron Device Lett., vol. 39, no. 9, pp. 1358–1361, 2018.
[7] M. K. Anvarifard, “An impressive structure containing triple trenches for RF power performance (TT-SOI-MESFET),” J. Comput. Electron., vol. 17, no. 1, pp. 230–237, 2017.
[8] M. Mehrad, M. Zareiee, “Improved device performance in nano scale transistor: an extended drain SOI MOSFET,” ECS Journal of Solid-State Science and Technology, vol. 5, M74, 2016.
[9] M. Zareiee, “A novel high-performance nano-scale MOSFET by inserting Si3N4 layer in the channel,” Superlattices and Microstructures, vol. 88, pp. 254-261, 2015.
[10] M. Schwarz, A. Kloes, “Analysis and performance study of III-V Schottky barrier double-gate MOSFETs using a 2-D analytical model,” IEEE Trans. on Electron Devices, vol. 63, pp. 2757-2763, 2016.
[11] M. Zareiee, “A new architecture of the dual gate transistor for the analog and digital applications,” AEU-International Journal of Electronic and Communications, vol. 100, pp. 114-118, 2019.
[12] J. E. Pakaree, M. Srivastava, “Realization with fabrication of double-gate MOSFET based differential amplifier, Microelectronics Journal, vol. 91, pp. 70-83, 2019.
[13] Z. Aghaeipour, A. Naderi, “Embedding two p+ pockets in the buried oxide of nano silicon on insulator MOSFETs: controlled short channel effects and electric field,” Silicon, vol. 12, pp. 2611-2618, 2020.
[14] N. Sharan, S. Mahapatra, “Nonquasi-static charge model for common double-gate MOSFETs adapted to gate oxide thickness asymmetry,” IEEE Tran. On Electron Devices, vol. 60, pp. 2419-2422, 2013.
[15] Device Simulator ATLAS, Silvaco, International, 2018.
[16] Atlas User’s Manual, Santa Clara, CA: Silvaco International, 2016. | ||
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