|تعداد مشاهده مقاله||7,638,013|
|تعداد دریافت فایل اصل مقاله||5,857,552|
Novel Drain Recessed Oxide SOI-MOSFET For Reduction of Short-Channel-Effects
|Computational Sciences and Engineering|
|دوره 2، شماره 2، آذر 2022، صفحه 211-216 اصل مقاله (267.15 K)|
|نوع مقاله: Original Article|
|شناسه دیجیتال (DOI): 10.22124/cse.2023.23783.1045|
|Mohammad Kazem Anvarifard*|
|Department of Engineering Sciences, Faculty of Technology and Engineering, East of Guilan, University of Guilan, Rudsar-Vajargah, Iran.|
|Since the device performance is degraded with the elapsed time, it is essential to develop the novel device for enhancing the reliability. Hence, a modification inside the drain region of the SOI-MOSFET structure has been performed. A region oxide has been recessed in the drain in order to modify the electric field owing to dielectric permittivity change. The simulation results obtained by SILVACO showed the improvement of the short-channel effects in the terms of drain-induced barrier lowering, hot-carrier effects and threshold voltage fluctuation as compared to the conventional structure.|
|SOI-MOSFET؛ Short channel effect؛ Threshold voltage؛ Recessed oxide|
 Ohno, Y. Kado, M. Harada, T. Tsuchiya, IEEE Transaction on Electron Devices 42 (1995) 1481–1486.
 A. Orouji, M. J. Kumar, MicroelectronicEngineering 83 (2006) 409-414.
 Kim, J. G. Fossum, IEEE Transaction on Electron Devices48 (2001) 294-299.
 Jhaveri, V. Nagavarapu, J. C. S. Woo, IEEE Transaction on Electron Devices56 (2009) 93-99.
 A.Majumdar, C. Ouyang, S. J. Koester, W. Haensch, IEEE Transaction on Electron Devices 57 (2010) 2067-2072.
 Ramezani and A. A. Orouji, "Investigation of veritcal graded channel doping in nanoscale fully-depleted SOI-MOSFET," Superlattices and Microstructures, vol. 98, pp. 359-370, 2016.
 Vimala and C. Usha, "Modeling of Source Pocket Engineered PNPN Tunnel FET on High-K Buried Oxide (H-BOX) Substrate for Improved ON Current," Silicon, pp. 1-7, 2022.
 Singh, A. Sharma, V. Kumar, P. Umar, A. K. Rao, and A. K. Singh, "Investigation of N+ SiGe juntionless vertical TFET with gate stack for gas sensing application," Applied Physics A, vol. 127, no. 9, pp. 1-11, 2021.
 International device simulation software, SILVACO TCAD, 2010.
 International technology roadmap for semiconductor. Availablefromhttp://public.itrs.net.
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